The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that extracts a clock signal and a data signal from a received high-speed serial signal.
In recent years, there has commonly been used serial communication with serial signals between electronic devices or between semiconductor devices. The serial communication is used in SATA (Serial ATA), USB (Universal Serial Bus), a wired LAN (Local Area Network), and the like. In the serial communication, the speed (frequency) of a transmission signal has recently been enhanced significantly, which disadvantageously causes a signal loss in a transmission line. For this reason, a reception circuit for serial communication receives a signal, using a correction circuit such as a decision feedback equalizer (DFE).
In the decision feedback equalizer, the stabilization result of a currently receiving data value needs to be fed the decision feedback equalizer, the time allowed for the process of feeding back the determination result is restricted within 1 UI (Unit Interval). For this reason, the decision feedback equalizer disadvantageously cannot deal with the enhanced speed of the transmission signal. Accordingly, to ease the restriction of the time required for feedback, a loop-unrolling-based decision feedback equalizer is proposed. The loop-unrolling equalizes an input signal speculatively without feeding back the first tap data value. Accordingly, by using the loop-unrolling-based decision feedback equalizer, it is possible to extend the time allowed for feedback to, e.g., 2 UI. Patent Document 1 and Non-patent Document 1 disclose examples of the loop-unrolling-based decision feedback equalizer.
The equalizer disclosed in Patent Document 1 includes first waveform equalization processing means and second waveform equalization processing means which alternately perform waveform equalization processing on a plurality of successively inputted signals. In the equalizer of Patent Document 1, the first waveform equalization processing means and the second waveform equalization processing means each add a value obtained by multiplying a value a indicating the determination result of the second last input signal and a value b indicating the determination result of the fourth last input signal by a constant w2 to the input signal subject to waveform equalization processing, thereby performing the waveform equalization processing. Further, Non-patent Document 1 discloses an example of performing equalization processing based on a value indicating the determination result of the second last or older input signal, as in Patent Document 1.